DMD Maskless Lithography for MEMS Prototyping: A Practical Selection Guide

1. Define the MEMS learning loop

List the design variables that will change: beam width, gap, anchor, electrode, membrane opening, etch window or release geometry. A DMD workflow is valuable when the team can revise the layout and expose a new coupon without ordering a new mask. Quantify the time from CAD revision to inspected sample and include design conversion, coating, exposure, development and measurement.

A prototype tool should also support traceability. Keep layout revision, recipe, substrate, resist, dose, focus, alignment marks and inspection image together. This lets the team tell whether a device change came from the layout or from process drift.

2. Map features to optical and profile needs

Separate binary features from profile-sensitive structures. Lines, gaps and openings may need uniform CD, while lenses, ramps, membranes or fluidic relief may need grayscale dose control and profile metrology. Record the smallest and largest geometry, equal line/space, edge slope, height or depth and the inspection instrument.

If the device has a nanoscale junction or dense critical feature, mark that layer for a separate technology review. DMD can handle broad microscale patterns efficiently, while EBL may be reserved for critical features. A hybrid process is useful only when marks, coordinate transfer and resist handoff are planned.

3. Choose the ZML platform by sample and control

ZML10A is positioned as a compact R&D system for rapid prototyping, MEMS and microfluidics with documented 385/405 nm exposure and up to 4-inch samples. ZML100A adds active autofocus and motorized objective control for workflows that need focus and overlay support. ZML200A is the family route when the project needs up to 8-inch substrates.

Compare the platform using the same device, resist, overlay and throughput conditions. The largest sample is not the only driver; objective working distance, thickness, flatness, mark visibility, focus variation and service access may be more important for a MEMS stack.

4. Build alignment into the MEMS layout

MEMS layers often mix a large device outline with small electrodes, marks or release windows. Place alignment marks near the critical layer and protect them through the resist and etch sequence. Define wafer orientation, chuck datum, file origin, scale and transform. A mark map is a practical interface between design, exposure and metrology.

Measure overlay on the actual substrate and topography. A mark that is visible on a flat coupon may disappear under a thick resist or after a deep etch. Keep a record of which layer owns each mark and how it is located by the selected objective or alignment routine.

5. Qualify resist, substrate and release compatibility

Specify substrate material, thickness, bow, surface treatment, resist, bake, wavelength, dose and development. MEMS flow can add hard masks, etch, metal lift-off, bonding or release steps that change the required resist profile. The supplier should demonstrate the process result or identify the development work still required.

Track contamination and handling. A prototype may move between coating, exposure, inspection and etch without the controlled packaging of a production fab. Define cleaning, storage, edge exclusion and operator steps so the process learning is reproducible.

6. Report throughput as iteration time

For MEMS, the useful metric is often the time to an inspected, measurable device rather than exposure seconds. Record file preparation, alignment, focus, exposure, development, inspection and rework. Compare sparse and dense patterns because DMD exposure time and process risk can change with pattern area and dose.

Ask for a representative weekly workload and a sample recipe. Include objective, resolution, wavelength, pattern density and operator steps. A tool that is fast on a small coupon may not deliver faster learning if every thick-resist layer requires lengthy focus or inspection.

• CAD-to-file conversion
• Load, align and focus
• Exposure and development
• Inspection, analysis and revision

7. Define the prototype acceptance coupon

Use a coupon that includes beams, gaps, electrodes, openings, alignment marks, profile structures and a dense feature. Measure CD, overlay, profile, defects and repeatability with the facility's instruments. Keep the same recipe and coordinate system across design iterations so results remain comparable.

Agree what is a platform acceptance result and what is a device-development result. The former should be repeatable at installation; the latter may evolve as the process matures. Document the handoff to an EBL step if critical features are split between tools.

8. Send the MEMS use case to the supplier

Provide layout examples, feature and profile targets, sample matrix, resist, wavelength, overlay, inspection, iteration time, environment and service constraints. Ask for configuration-specific results, file workflow, alignment method, throughput conditions and an acceptance coupon.

SENFU can match a MEMS prototype requirement to the ZML family and identify when a hybrid DMD/EBL process is more practical. The output should be a documented learning loop that the research team can repeat and the procurement team can defend.

9. Protect the learning loop from hidden variation

MEMS iteration is valuable only when one design change can be separated from process drift. Keep the same wafer orientation, chuck datum, mark map, resist preparation, exposure file and inspection coordinates while changing the geometry under study. Record coating lot, bake, dose, focus, development and operator. If a feature improves, the team should be able to explain whether the improvement came from the layout or from an uncontrolled process change.

Define a small control coupon that travels with each prototype run. Include a line/space feature, an alignment mark, a profile structure and a representative device fragment. Trend CD, overlay, profile and defect observations against the control. When a layer moves to EBL or another facility, transfer the coordinate and mark record with the job. This creates a practical bridge from university-style iteration to a reproducible engineering process and gives procurement evidence for the next tool decision.

Use the control record to decide when a prototype is ready for the next unit operation. A release or bonding step may magnify a small overlay or profile error, while a large device outline may hide a local defect. Set a review gate for the critical layer, archive the inspected coupon and record any process-development exception. The gate does not slow experimentation; it prevents an untracked change from being mistaken for a better lithography platform.

• Fixed control coupon and coordinates
• Design revision versus process revision
• Operator, lot and warm-up record
• Cross-tool mark and data handoff